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发表于 2009-10-11 15:44:48
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CPU core
The CPU core is a two-way superscalar in-order RISC processor. It implements the MIPS-III instruction set architecture (ISA) and much of MIPS-IV in addition to a custom 128-bit single instruction multiple data (SIMD) instruction set developed by Sony. The custom instruction set consists of 107 instructions for operating on four 32-bit, eight 16-bit or sixteen 8-bit integers simultaneously. Instructions defined include: add, subtract, multiply, divide, min/max, shift, logical, leading-zero count, 128-bit load/store and 256-bit to 128-bit funnel shift in addition to some not described by Sony for competitive reasons.
The MIPS-based core consists of two arithmetic logic units (ALUs) and a floating point unit (FPU). The integer units are 64-bit, but the FPU was single-precision, or 32-bit. The custom instruction set was implemented by grouping the two 64-bit integer units. Both the integer and floating-point pipelines are both six stages long. To support the custom instruction set, the integer registers are 128 bits wide.
http://en.wikipedia.org/wiki/Emotion_Engine
可以认为EMOTION_ENGINE是128位CPU了. 至少从程序员角度来看, 它具有128bit的通用寄存器, 128位的ALU, 128位的load/store指令.
但实际上EE的128位ALU是由两个64位ALU组成的, 当使用64位指令集的时候可以分开来在两条流水线中用的. |
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